1. Technical Field
The disclosed embodiments relate to all-digital phase-locked loops (ADPLLs).
2. Background Information
FIG. 1 (Prior Art) is a block diagram of one example of a type of all-digital phase-locked loop (ADPLL) called a time-to-digital converter (TDC) PLL 1. Such a TDC PLL may, for example, be used to generate a local oscillator signal LO in the local oscillator of the transmitter of a cellular telephone. TDC PLL 1 involves a loop filter 2 that outputs a stream of multi-bit digital tuning words. A Digitally Controlled Oscillator (DCO) 3 receives a digital tuning word and outputs a corresponding signal DCO_OUT whose frequency is determined by the digital tuning word. DCO 3 may, for example, receive a reference clock signal REF such that it changes the frequency of DCO_OUT synchronously with respect to clock signal REF. An accumulator 4 increments each period of DCO_OUT, and the value of the accumulator is latched into latch 5 synchronously with the reference clock signal REF. A reference phase accumulator 6 increments by the value on its input leads 7. Reference phase accumulator 6 also increments synchronously with the reference clock signal REF. The value accumulated in accumulator 6 is supplied via lines 8 to a subtractor 9. The output of an adder 10 is supplied via lines 11 to subtractor 9. Subtractor 9, which is also referred to as a phase detector, subtracts the value on lines 11 from the value on lines 8 and supplies the resulting error value in the form of a digital word onto lines 12 and to loop filter 2.
The value on input leads 7 by which accumulator 6 increments is the sum of a modulation frequency control value on lines 13, a channel frequency control integer value on lines 14, and a channel frequency control fractional value on lines 15. The fractional value 15 is changed over time by a delta-sigma modulator 21. In this particular example, two point modulation is used so the modulation frequency control value on lines 13 is scaled by block 19 and is injected into the control loop at a second modulation point at adder 20. The value on lines 11 is the sum of an integer portion output by latch 5 as well as a fractional portion on lines 16. A time-to-digital converter 17 produces a digital output timestamp representing the time difference between an edge of the signal DCO_OUT and an edge of the reference clock signal REF. The reference clock signal REF in this example has a fixed, but significantly lower frequency than DCO_OUT. The timestamps output by TDC 17 are normalized by a normalization circuit 18 to generate the fractional portion on lines 16. The control loop operates to keep the values on lines 8 and 11 locked to one another and substantially identical.
Although the conventional ADPLL of FIG. 1 works well in the cellular telephone transmitter application, the frequency of the signal DCO_OUT changes at discrete times. These discrete times are equally spaced in time. This introduces what is known at as a “digital images”. These digital images are spectral components of the local oscillator output signal LO that are not at the desired LO main frequency. As the frequency of the reference clock REF increases, the digital images move farther away in frequency from the LO main frequency, and the digital images get smaller in power. Increasing the frequency of the reference clock REF therefore reduces the digital image noise problem. For most cellular telephone protocols, there is a specification that sets the maximum allowed noise allowed outside the channel in which the cellular telephone is transmitting. For GSM (Global System for Mobile Communications) applications, for example, it is generally necessary to increase the frequency of REF to be higher than about 40 megahertz so that the digital images are of low enough magnitude. Increasing the frequency of the reference clock REF, however, increases the amount of switching in the PLL circuitry and therefore increases power consumption.